1. Field of the Invention
This invention relates to clocking in electronic systems and more particularly to managing jitter in high speed clocking environments.
2. Description of the Related Art
High speed clocks are used in transmission systems to synchronize the flow of data. Those high speed clocks may include jitter, which should be managed to prevent bit errors. Jitter is the variation in clock output frequency from a desired output frequency and can occur for a number of reasons. For example, jitter may be caused by noise introduced into the system from any of a variety of sources. A critical area of jitter management is in the transmit path of an optical/electrical interface where the outgoing light pulses typically have jitter within tight system requirements.
A typical transmit path of an electrical/optical interface is illustrated in FIG. 1. Low speed data that is supplied by the system on node 101 is written into a First In First Out (FIFO) memory 103 using a low speed clock supplied on node 105. A clock multiplier unit (CMU) 107 generates a high speed clock on node 109. The CMU 107 is configured as a phase-locked loop (PLL) and uses a lower speed reference clock supplied on node 111 as its input, which is multiplied to provide the high speed clock on node 109. The high speed clock generated by the CMU 107 is used to read data out of FIFO 103 and send it to a laser driver and laser 113 for optical transmission.
A typical CMU utilizes a wideband PLL, which passes virtually all of the jitter present on its input (the reference clock) to the output. Thus, a very low jitter clock reference source, such as a high quality crystal oscillator, has been used in order to meet the transmit jitter generation requirements. In this context “wideband” is defined as a PLL with closed loop bandwidth above or at the high end of the jitter frequencies of interest for output jitter generation. For example, for an OC-48 Synchronous Optical Network (SONET) system, having a data rate of approximately 2.5 GHz, transmit jitter is specified for jitter frequencies from 12 KHz to 20 MHz. A wideband PLL typically used in such a system would have a closed loop bandwidth that encompasses a substantial portion of the frequency range of the jitter frequencies of interest, e.g., a closed loop bandwidth of 15 MHz.
The need for a high precision clock source adds expense to a system both in terms of the cost of a high precision crystal oscillator, particularly at frequencies above 100 MHz, as well as additional complexity in design and board layout. In addition, reference clocks are often distributed across backplanes, making low jitter difficult to obtain. It would be desirable to relax the tight jitter requirements of the reference clock in order to remove the need for a high precision clock source, which would simplify system design and implementation and reduce its cost.